The present invention relates to a buffer control circuit of a memory device, and more particularly, to a buffer control circuit of a memory device, which can minimize an operating current consumption of a dynamic random access memory (DRAM) by efficiently controlling a buffer in an auto-refresh mode.
Generally, a system includes an operation processor and a memory device. To achieve a high-speed of operation or signal processing, the operation processor has to process a large number of data bits at a time. Further, a large quantity of data to be processed must be supplied to the operation processor in accordance with its operation process. Therefore, an operation speed of the system is determined by whether data required can be supplied to the memory device at an appropriate time or not.
When a large quantity of data is outputted from the memory device by a switching operation in order to increase the operation speed of the system, a large amount of current is supplied from a power line to a switching element. At this point, the current consumed generates switching noise due to parasitic components of the power line, resulting in delay and distortion of output data. When output data of a large number of bits are switched in one direction and output data of a small number of bits are switched in another direction, e.g., an opposite direction, a delay time of the output data becomes different according to the switching direction of the output data. This causes a skew between the output data.
The skew increases as the number of bits of the output data is larger, parasitic components are larger, and the operating speed is higher The skew means a timing mismatch between data. In a read operation or a write operation, a data training is performed for controlling the skew between data. The data training represents a technique to control the skew between data by using data pattern known to a controller and a memory device. The data training may be classified into a write training and a read training.
A unit cell of a dynamic random access memory (DRAM) consists of one transistor and one capacitor, and data is stored in the capacitor. However, since the capacitor formed on a semiconductor substrate is not completely electrically isolated from peripheral elements, the stored data are not retained, that is, electric charges are discharged. In other words, leakage current is generated and thus data of the memory cell may be damaged. Therefore, the memory device periodically performs a refresh operation to maintain electric charges stored in the capacitor.
The memory device with a refresh mode performs a refresh operation while sequentially changing internal addresses in response to an external command. More specifically, when the memory device enters a refresh mode in response to an external command, a row address sequentially increases in every constant period and a word line is selected. Electric charges stored in the capacitor corresponding to the word line are amplified by a sense amplifier and are again stored in the capacitor. The stored data can be retained without damage through the refresh process.
The conventional memory device controls the disabling of data input/output buffers by performing no data training operation in the auto-refresh mode. Since it is unnecessary to control the enabling of the data buffers, a current for controlling the data buffers is not consumed.
Meanwhile, the data input/output buffers are required to be enabled even in the auto-refresh mode because a memory device needs to perform a data training operation in an initialization mode and an auto-refresh mode. That is, if the data training operation is performed, all data input/output buffers are ready to receive data. Therefore, all data input/output buffers must be in an enabled state during the auto-refresh mode. Further, the data clock controller, the command decoder, and the command clock controller must maintain an enabled state in order for the data training operation.
However, the current consumption increases when the data input/output buffers and other elements are enabled during the auto-refresh mode. If the memory device enters the auto-refresh mode, the data input/output buffers and other elements are enabled even in the low power mode, thus increasing the current consumption.